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1 for more information www.linear.com/ltc6752 typical a pplica t ion fea t ures descrip t ion 280mhz, 2.9ns comparator family with rail-to-rail inputs and cmos outputs the lt c ? 6752 is a family of very high speed comparators capable of supporting toggle rates up to 280mhz. these comparators exhibit low propagation delays of 2.9ns, and fast rise/fall times of 1.2ns. there are a total of 5 members in the ltc6752 family, with different options for separate input and output supplies , shutdown, output latch, adjust - able hysteresis, complementary outputs, and package. the ltc6752 comparators have rail-to-rail inputs that operate from 2.45v, up to 3.5v or 5.25v, depending on the option. the outputs are cmos and the separate supply options can operate down to 1.71v, allowing for directly interfacing to 1.8v logic devices. the low propagation delay of only 2.9ns combined with low dispersion of only 1.8ns (10mv to 125mv overdrive variation) makes these comparators an excellent choice for critical timing applications. similarly, the fast toggle rate and the low jitter of 4.5ps rms (100mv p-p , 100mhz input) make the ltc6752 family ideally suited for high frequency line driver and clock recovery circuits. a pplica t ions n very high toggle rate: 280mhz n low propagation delay: 2.9ns n rail-to-rail inputs extend beyond both rails n output current capability: 22ma n low quiescent current: 4.5ma n features within the ltc6752 family: n 2.45v to 5.25v input supply and 1.71v to 3.5v output supply (separate supply option) n 2.45v to 3.5v supply (single supply option) n shutdown pin for reduced power n output latch and adjustable hysteresis n complementary outputs n packages: tsot-23, sc70, msop, 3mm 3mm qfn n direct replacement for adcmp60x family n fully specifed from C55c to 125c n clock and data recovery n level shifting n high speed data acquisition systems n window comparators n high speed line receivers n fast crystal oscillators n time of flight measurements n time domain refectometry l, lt , lt c , lt m , linear technology and the linear logo are registered trademarks of analog devices, inc. all other trademarks are the property of their respective owners. 500mv/div ?in +in q 50ns/div 6752 t01a high speed differential line receiver with excellent common mode rejection v cc = 5v ? + q 6752 t01a small differential signal with large common mode component v ee +in ?in ltc6752-2 v dd = 2.7v ltc 6752/ ltc 6752-1/ ltc 6752 -2/ ltc 6752-3/ ltc 6752 -4 6752fc
2 for more information www.linear.com/ltc6752 a bsolu t e maxi m u m r a t ings total supply voltage (v cc to v ee ) ( ltc 6 752 -2/ ltc 6752 -3/ ltc 6752 -4) .................... 5 .5 v ( ltc 6 752 / ltc 6752 -1) .......................................... 3 .6 v total supply voltage (v dd to v ee ) ............................ 3. 6 v input current (+ in , C in , shdn , le / hyst ) ( note 2) ................................................................ 1 0 ma output current (q, q ) ( note 3) ............................ 50 ma specified temperature range ( note 4) ltc 6752 i ............................................. C4 0 c to 85 c ltc 6752 h .......................................... C 40 c to 125 c ltc 6 752 mp ....................................... C 55 c to 125 c storage temperature range .................. C 65 c to 125 c maximum junction temperature ( note 3) ............. 150 c lead temperature soldering (10 s) ........................ 30 0 c (note 1) ltc6752 ltc6752-1 ltc6752-2 q 1 v ee 2 top view s5 package 5-lead plastic tsot-23 +in 3 5 v cc 4 ?in t jmax = 150c, ja = 215c/w (note 3) q 1 v ee 2 +in 3 6 v cc 5 le /hyst 4 ?in top view sc6 package 6-lead plastic sc70 with latching/adjustable hysteresis t jmax = 150c, ja = 270c/w (note 3) 1 2 3 4 v cc +in ?in shdn 8 7 6 5 v dd q v ee le /hyst top view ms8 package 8-lead plastic msop t jmax = 150c, ja = 163c/w (note 3) ltc6752-3 ltc6752-4 12 11 10 4 5 6 top view 13 v ee ud package 12-lead (3mm 3mm) plastic qfn 7 8 9 3 2 1v dd v cc v ee v ee le /hyst shdn q nc q +in nc ?in t jmax = 150c, ja = 68c/w (note 3) exposed pad (pin 13) is v ee , must be soldered to pcb q 1 v ee 2 +in 3 6 v cc 5 v dd 4 ?in top view sc6 package 6-lead plastic sc70 with separate input/output supplies t jmax = 150c, ja = 270c/w (note 3) p in c on f igura t ion table 1. features and part numbers part # latching/adjustable hysteresis separate input/ output supplies shutdown complementary outputs package offering ltc6752 tsot-23-5 ltc6752-1 l sc70-6 ltc6752-2 l l l ms8 ltc6752-3 l l l l 3mm 3mm qfn ltc6752-4 l sc70-6 ltc 6752/ ltc 6752-1/ ltc 6752 -2/ ltc 6752-3/ ltc 6752 -4 6752fc
3 for more information www.linear.com/ltc6752 lead free finish tape and reel (mini) tape and reel part marking* package description specified temperature range ltc6752is5#trmpbf ltc6752is5#trpbf ltgkt 5-lead plastic tsot-23 C40c to 85c ltc6752hs5#trmpbf ltc6752hs5#trpbf ltgkt 5-lead plastic tsot-23 C40c to 125c ltc6752mps5#trmpbf ltc6752mps5#trpbf ltgkt 5-lead plastic tsot-23 C55c to 125c ltc6752isc6-1#trmpbf ltc6752isc6-1#trpbf lgqk 6-lead plastic sc-70 C40c to 85c ltc6752hsc6-1#trmpbf ltc6752hsc6-1#trpbf lgqk 6-lead plastic sc-70 C40c to 125c ltc6752isc6-4#trmpbf ltc6752isc6-4#trpbf lgqm 6-lead plastic sc-70 C40c to 85c ltc6752hsc6-4#trmpbf ltc6752hsc6-4#trpbf lgqm 6-lead plastic sc-70 C40c to 125c trm = 500 pieces. *temperature grades are identified by a label on the shipping container. lead free finish tape and reel part marking* package description specified temperature range ltc6752ims8-2#pbf ltc6752ims8-2#trpbf ltgkw 8-lead plastic msop C40c to 85c ltc6752hms8-2#pbf ltc6752hms8-2#trpbf ltgkw 8-lead plastic msop C40c to 125c ltc6752iud-3#pbf ltc6752iud-3#trpbf lgkv 12-lead plastic qfn (3mm 3mm) C40c to 85c ltc6752hud-3#pbf ltc6752hud-3#trpbf lgkv 12-lead plastic qfn (3mm 3mm) C40c to 125c consult ltc marketing for parts specified with wider operating temperature ranges . * the temperature grade is identified by a label on the shipping container. consult ltc marketing for information on nonstandard lead based finish parts. for more information on lead free part marking , go to: http://www.linear.com/leadfree/ for more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ some packages are available in 500 unit reels through designated sales channels with #trmpbf suffix. e lec t rical c harac t eris t ics (v cc = 2.5v, v dd = 2.5v, v ee = 0). the l denotes the specifications which apply over the specified temperature range, otherwise specifications are at t a = 25c. le/hyst, shdn pins floating, c l = 5pf, v overdrive = 50mv, Cin = v cm = 300mv, +in = Cin + v overdrive , 150mv step size unless otherwise noted. symbol parameter conditions min typ max units v cc - v ee supply voltage (note 5) ltc6752/ltc6752-1 (total supply) ltc6752-2/ltc6752-3/ltc6752-4 ( input stage) l l 2.45 2.45 3.5 5.25 v v v dd - v ee output stage supply voltage (note 5) ltc6752-2/ltc6752-3/ltc6752-4 l 1.71 3.5 v v cmr input voltage range (note 7) l v ee C 0.2 v cc + 0.1 v v os input offset voltage (note 6) l C5.5 C8.5 1.2 5.5 8.5 mv mv tcv os input offset voltage drift l 18 v/c v hyst input hysteresis voltage (note 6) le/hyst pin floating 5 mv c in input capacitance 1.1 pf r dm differential mode resistance 57 k r cm common mode resistance 6.4 m i b input bias current v cm = v ee + 0.3v l C3.8 C4 C1.35 a a v cm = v cc C 0.3v l 0.3 1.25 2.1 a a i os input offset current l C0.75 0.1 0.75 a cmrr_ lvcm common mode input range, low v cm region v cm = v ee C 0.2v to v cc C 1.5v l 51 46 69 db db cmrr _fr common mode rejection ratio (measured at extreme ends of v cmr ) v cm = v ee C 0.2v to v cc + 0.1v l 50 45.5 65 db db o r d er i n f or m a t ion http://www .linear.com/product/ltc6752#orderinfo ltc 6752/ ltc 6752-1/ ltc 6752 -2/ ltc 6752-3/ ltc 6752 -4 6752fc
4 for more information www.linear.com/ltc6752 e lec t rical c harac t eris t ics (v cc = 2.5v, v dd = 2.5v, v ee = 0). the l denotes the specifications which apply over the specified temperature range, otherwise specifications are at t a = 25c. le/hyst, shdn pins floating, c l = 5pf, v overdrive = 50mv, Cin = v cm = 300mv, +in = Cin + v overdrive , 150mv step size unless otherwise noted. symbol parameter conditions min typ max units psrr_v cc input power supply rejection ratio v cm = 0.3v, v dd = 2.5v, v cc varied from 2.45v to 5.25v (ltc6752-2/ltc6752-3/ltc6752-4) l 59 57 74 db db t otal power supply rejection ratio v cm = 0.3v, v cc varied from 2.45v to 3.5v (ltc6752/ltc6752-1) l 53 51 73 db db psrr _v dd output power supply rejection ratio v cm = 0.3v, v dd varied from 1.71v to 3.5v (ltc6752-2/ltc6752-3/ltc6752-4) l 56 51 71 db db a vol open loop gain ltc6752-1/ltc6752-2/ltc6752-3, hysteresis removed (note 12) 6000 v/v v oh output high voltage (amount below v dd (ltc6752-2/ltc5752-3/ltc6752-4), v cc (ltc6752/ltc6752-1)) i source = 8ma l 130 260 340 mv mv v ol output low voltage (referred to v ee ) i sink = 8ma l 200 340 400 mv mv i sc output short-circuit current source l 16 12 30 ma ma sink l 15 9 22 ma ma i vcc v cc supply current, device on ltc6752/ltc6752-1 l 4.5 5.0 5.9 ma ma ltc 6752-2/ltc6752-3/ltc6752-4 l 1.9 2.25 2.5 ma ma i vdd v dd supply current, device on ltc6752-2/ltc6752-4 l 2.6 3.2 3.4 ma ma ltc 6752-3 l 4.3 4.75 5.2 ma ma i total total supply current, device on ltc6752/ltc6752-1/ltc6752-2/ltc6752-4 l 4.5 5.0 5.9 ma ma ltc 6752-3 l 6.2 6.65 7.7 ma ma t r , t f rise/fall time 10% to 90% 1.2 ns t pd propagation delay (note 8) v overdrive = 50mv l 2.9 5 5.5 ns ns t skew propagation delay skew, rising to falling transition (note 9) 300 ps t odd overdrive dispersion (note 8) overdrive varied from 10mv to 125mv 1.8 ns t cmd common mode dispersion v cm varied from v ee C 0.2v to v cc + 0.1v 240 ps tr toggle rate (note 11) 100mv p-p input, ltc6752/ltc6752-1/ ltc6752 - 2/ltc6752-4 100mv p-p input, ltc6752-3 280 250 mhz mhz t jitter rms jitter v in = 100mv p-p , f in = 100mhz, jitter bw = 10hz C 50mhz f in = 61.44mhz, jitter bw = 10hz C 30.72mhz f in = 10mhz, jitter bw = 10hz C 5mhz 4.5 6.0 30 ps ps ps ltc 6752/ ltc 6752-1/ ltc 6752 -2/ ltc 6752-3/ ltc 6752 -4 6752fc
5 for more information www.linear.com/ltc6752 e lec t rical c harac t eris t ics (v cc = 2.5v, v dd = 2.5v, v ee = 0). the l denotes the specifications which apply over the specified temperature range, otherwise specifications are at t a = 25c. le/hyst, shdn pins floating, c l = 5pf, v overdrive = 50mv, Cin = v cm = 300mv, +in = Cin + v overdrive , 150mv step size unless otherwise noted. symbol parameter conditions min typ max units latching/adjustable hysteresis characteristics (ltc6752-1/ltc6752-2/ltc6752-3 only) v le/hyst le /hyst pin voltage open circuit l 1.05 1.25 1.45 v r hyst resistance looking into le/hyst le /hyst pin voltage < open circuit value l 15 20 25 k v hyst_ large hysteresis voltage v le/hyst = 800mv 40 mv v il_le latch pin voltage, latch guaranteed l 0.3 v v ih_le latch pin voltage, hysteresis disabled output not latched l 1.7 v i ih_le latch pin current high v le/hyst = 1.7v l 30 72 a i il_le latch pin current low v le/hyst = 0.3v l C70 C47 a t setup latch setup time (note 10) C2 ns t hold latch hold time (note 10) 2 ns t pl latch to output delay 7 ns shutdown characteristics (ltc6752-2/ltc6752-3 only) i sd_vcc shutdown mode input stage supply current v shdn = 0.6v l 400 585 620 a a i sd_vdd shutdown mode output stage supply current v shdn = 0.6v, ltc6752-2 l 185 340 380 a a v shdn = 0.6v, ltc6752-3 l 250 650 680 a a t sd shutdown time output hi-z 80 ns v ih_sd shutdown pin voltage high part guaranteed to be powered on l 1.3 v v il_sd shutdown pin voltage low part guaranteed to be powered off l 0.6 v t wakeup wake-up time from shutdown v od = 100mv, output valid 100 ns (v cc = 3.3v, v dd = 3.3v, v ee = 0). the l denotes the specifications which apply over the specified temperature range, otherwise specifications are at t a = 25c. le/hyst, shdn pins floating, c l = 5pf, v overdrive = 50mv, Cin = v cm = 300mv, +in = Cin + v overdrive , 150mv step size unless otherwise noted. symbol parameter conditions min typ max units v cc - v ee supply voltage (note 5) ltc6752/ltc6752-1 (total supply) ltc6752-2/ltc6752-3/ltc6752-4 ( input stage) l l 2.45 2.45 3.5 5.25 v v v dd - v ee output supply voltage (note 5) ltc6752-2/ltc6752-3/ltc6752-4 l 1.71 3.5 v v cmr input voltage range (note 7) l v ee C 0.2 v cc + 0.1 v v os input offset voltage (note 6) l C5.5 C9 1.2 5.5 9 mv mv tcv os input offset voltage drift l 18 v/c v hyst input hysteresis voltage (note 6) le/hyst pin floating 4.7 mv c in input capacitance 1.1 pf r dm differential mode resistance 57 k r cm common mode resistance 6.4 m i b input bias current v cm = v ee + 0.3v l C3.8 C4.1 C1.4 a a v cm = v cc C 0.3v l 0.33 1.5 2.3 a a i os input offset current l C0.75 0.1 0.75 a ltc 6752/ ltc 6752-1/ ltc 6752 -2/ ltc 6752-3/ ltc 6752 -4 6752fc
6 for more information www.linear.com/ltc6752 e lec t rical c harac t eris t ics (v cc = 3.3v, v dd = 3.3v, v ee = 0). the l denotes the specifications which apply over the specified temperature range, otherwise specifications are at t a = 25c. le/hyst, shdn pins floating, c l = 5pf, v overdrive = 50mv, Cin = v cm = 300mv, +in = Cin + v overdrive , 150mv step size unless otherwise noted. symbol parameter conditions min typ max units cmrr_ lvcm common mode input range, low v cm region v cm = v ee C 0.2v to v cc C 1.5v l 52 48 70 db db cmrr _fr common mode rejection ratio (measured at extreme ends of v cmr ) v cm = v ee C 0.2v to v cc + 0.1v l 50 46 66 db db psrr _v cc input power supply rejection ratio v cm = 0.3v, v dd = 3.3v,v cc varied from 2.45v to 5.25v (ltc6752-2/ltc6752-3/ltc6752-4) l 59 57 75 db t otal power supply rejection ratio v cm = 0.3v,v cc varied from 2.45v to 3.5v (ltc6752/ltc6752-1) l 53 51 73 db db psrr _v dd output power supply rejection ratio v cm = 0.3v, v dd varied from 1.71v to 3.5v (ltc6752-2/ltc6752-3/ltc6752-4) l 56 51 71 db db a vol open loop gain ltc6752-1/ltc6752-2/ltc6752-3,hysteresis removed (note 12) 7000 v/v v oh output high voltage (amount below v dd (ltc6752-2/ltc5752-3/ltc6752-4), v cc (ltc6752/ltc6752-1)) i source = 8ma l 81 200 300 mv mv v ol output low voltage (referred to v ee ) i sink = 8ma l 155 320 350 mv mv i sc output short-circuit current source l 35 30 70 ma ma sink l 20 15 39 ma ma i vcc v cc supply current, device on ltc6752/ltc6752-1 l 4.8 5.8 6.2 ma ma ltc 6752-2/ltc6752-3/ltc6752-4 l 1.9 2.35 2.55 ma ma i vdd v dd supply current, device on ltc6752-2/ltc6752-4 l 2.9 3.45 3.65 ma ma ltc 6752-3 l 4.75 5.35 5.75 ma ma i total total supply current, device on ltc6752/ltc6752-1/ltc6752-2/ltc6752-4 l 4.8 5.8 6.2 ma ma ltc 6752-3 l 6.6 7.7 8.3 ma ma t r , t f rise/fall time 10% to 90% 1.35 ns t pd propagation delay (note 8) v overdrive = 50mv l 3.00 5 5.5 ns ns t skew propagation delay skew, rising to falling transition (note 9) 600 ps t odd overdrive dispersion (note 8) overdrive varied from 10mv to 125mv 1.8 ns t cmd common mode dispersion v cm varied from v ee 0.2v to v cc + 0.1v 240 ps tr toggle rate (note 11) 100mv p-p input 215 mhz t jitter rms jitter v in = 100mv p-p , f in = 100mhz, jitter bw = 10hz C 50mhz f in = 61.44mhz, jitter bw = 10hz C 30.72mhz f in = 10mhz, jitter bw = 10hz C 5mhz 4.8 5.8 29 ps ps ps ltc 6752/ ltc 6752-1/ ltc 6752 -2/ ltc 6752-3/ ltc 6752 -4 6752fc
7 for more information www.linear.com/ltc6752 e lec t rical c harac t eris t ics (v cc = 3.3v, v dd = 3.3v, v ee = 0). the l denotes the specifications which apply over the specified temperature range, otherwise specifications are at t a = 25c. le/hyst, shdn pins floating, c l = 5pf, v overdrive = 50mv Cin = v cm = 300mv, +in = Cin + v overdrive , 150mv step size unless otherwise noted. symbol parameter conditions min typ max units latching/adjustable hysteresis characteristics (ltc6752-1/ltc6752-2/ltc6752-3 only) v le/hyst le /hyst pin voltage open circuit l 1.05 1.25 1.45 v r hyst resistance looking into le/hyst le /hyst pin voltage < open circuit value l 15 20 25 k v hyst_ large hysteresis voltage v le/hyst = 800mv 40 mv v il_le latch pin voltage, latch guaranteed l 0.3 v v ih_le latch pin voltage, hysteresis disabled output not latched l 1.7 v i ih_le latch pin current high v le/hyst = 1.7v l 30 72 a i il_le latch pin current low v le/hyst = 0.3v l C70 C47 a t setup latch setup time (note 10) C2 ns t hold latch hold time (note 10) 2 ns t pl latch to output delay 7 ns shutdown characteristics (ltc6752-2/ltc6752-3 only) i sd_vcc shutdown mode input stage supply current v shdn = 0.6v l 430 600 660 a a i sd_vdd shutdown mode output stage supply current v shdn = 0.6v, ltc6752-2 l 200 420 450 a a v shdn = 0.6v, ltc6752-3 l 300 700 800 a a t sd shutdown time output hi-z 80 ns v ih_sd shutdown pin voltage high part guaranteed to be powered on l 1.3 v v il_sd shutdown pin voltage low part guaranteed to be powered off l 0.6 v t wakeup wake-up time from shutdown v od = 100mv, output valid 100 ns (v cc = 5v, v dd = 1.8v, v ee = 0, ltc6752-2/ltc6752-3/ltc6752-4 only). the l denotes the specifications which apply over the specified temperature range, otherwise specifications are at t a = 25c. le/hyst, shdn pins floating, c l = 5pf, v overdrive = 50mv, Cin = v cm = 300mv, +in = Cin + v overdrive , 150mv step size unless otherwise noted. symbol parameter conditions min typ max units v cc - v ee input supply voltage (note 5) l 2.45 5.25 v v dd - v ee output supply voltage (note5) l 1.71 3.5 v v cmr input voltage range (note 7) l v ee C 0.2 v cc + 0.1 v v os input offset voltage (note 6) l C5.5 C9 1.2 5.5 9 mv mv tcv os input offset voltage drift l 14 v/c v hyst input hysteresis voltage (note 6) le/hyst pin floating 5.2 mv c in input capacitance 1.1 pf r dm differential mode resistance 57 k r cm common mode resistance 6.4 m i b input bias current v cm = v ee + 0.3v l C3.9 C4.2 C1.5 a a v cm = v cc C 0.3v l 0.36 1.6 2.5 a a ltc 6752/ ltc 6752-1/ ltc 6752 -2/ ltc 6752-3/ ltc 6752 -4 6752fc
8 for more information www.linear.com/ltc6752 e lec t rical c harac t eris t ics (v cc = 5v, v dd = 1.8v, v ee = 0, ltc6752-2/ltc6752-3/ltc6752-4 only). the l denotes the specifications which apply over the specified temperature range, otherwise specifications are at t a = 25c. le/hyst, shdn pins floating, c l = 5pf, v overdrive = 50mv, Cin = v cm = 300mv, +in = Cin + v overdrive , 150mv step size unless otherwise noted. symbol parameter conditions min typ max units i os input offset current l C0.9 0.1 0.9 a cmrr_ lvcm common mode input range, low v cm region v cm = v ee C 0.2v to v cc C 1.5v l 54 51 70 db db cmrr _fr common mode rejection ratio (measured at extreme ends of v cmr ) v cm = v ee C 0.2v to v cc + 0.1v l 53 48 68 db db psrr _v cc input power supply rejection ratio v cm = 0.3v, v dd = 1.8v,v cc varied from 2.45v to 5.25v l 59 57 75 db psrr _v dd output power supply rejection ratio v cm = 0.3v, v dd varied from 1.71v to 3.5v l 57 51 71 db db a vol open loop gain ltc6752-2/ltc6752-3 hysteresis removed (note 12) 3500 v/v v oh output high voltage (amount below v dd ) i source = 5.5ma l 200 400 450 mv mv v ol output low voltage (referred to v ee ) i sink = 5.5ma l 200 400 550 mv mv i sc output short-circuit current source l 9 6.2 17 ma ma sink l 11 6.2 19 ma ma i vcc v cc supply current, device on l 2.1 2.65 2.85 ma ma i vdd v dd supply current, device on ltc6752-2/ltc6752-4 l 2.5 3 3.25 ma ma ltc 6752-3 l 3.4 4.4 4.8 ma ma i total total supply current, device on ltc6752-2/ltc6752-4 l 4.5 5.65 6.1 ma ma ltc 6752-3 l 6 7.05 7.65 ma ma t r , t f rise/fall time 10% to 90% 1.25 ns t pd propagation delay (note 8) v overdrive = 50mv l 3.4 5.3 5.7 ns ns t skew propagation delay skew, rising to falling transition (note 9) 400 ps t odd overdrive dispersion (note 8) overdrive varied from 10mv to 125mv 1.8 ns t cmd common mode dispersion v cm varied from v ee C 0.2v to v cc + 0.1v 240 ps tr toggle rate (note 11) 100mv p-p input, ltc6752-2/ltc6752-4 100mv p-p input, ltc6752-3 230 185 mhz mhz t jitter rms jitter v in = 100mv p-p , f in = 100mhz, jitter bw = 10hz C 50mhz f in = 61.44mhz, jitter bw = 10hz C 30.72mhz f in = 10mhz, jitter bw = 10hz C 5mhz 4.3 5.8 28 ps ps ps ltc 6752/ ltc 6752-1/ ltc 6752 -2/ ltc 6752-3/ ltc 6752 -4 6752fc
9 for more information www.linear.com/ltc6752 e lec t rical c harac t eris t ics (v cc = 5v, v dd = 1.8v, v ee = 0, ltc6752-2/ltc6752-3 only). the l denotes the specifications which apply over the specified temperature range, otherwise specifications are at t a = 25c. le/hyst, shdn pins floating, c l = 5pf, v overdrive = 50mv, Cin = v cm = 300mv, +in = Cin + v overdrive , 150mv step size unless otherwise noted. symbol parameter conditions min typ max units latching/adjustable hysteresis characteristics (ltc6752-2/ltc6752-3 only) v le/hyst le /hyst pin voltage open circuit l 1.05 1.25 1.45 v r hyst resistance looking into le/hyst le /hyst pin voltage < open circuit value l 15 20 25 k v hyst_ large modified input hysteresis voltage (note 2) v le/hyst = 800mv 40 mv v il_le latch pin voltage, latch guaranteed l 0.3 v v ih_le latch pin voltage, hysteresis disabled output not latched l 1.7 v i ih_le latch pin current high v le/hyst = 1.7v l 30 72 a i il_le latch pin current low v le/hyst = 0.3v l C70 C47 a t setup latch setup time (note 10) C2 ns t hold latch hold time (note 10) 2 ns t pl latch to output delay 7 ns shutdown characteristics (ltc6752-2/ltc6752-3 only) i sd_vcc shutdown mode input stage supply current v shdn = 0.6v l 500 650 750 a a i sd_vdd shutdown mode output stage supply current v shdn = 0.6v, ltc6752-2 l 170 400 450 a a v shdn = 0.6v, ltc6752-3 l 240 600 650 a a t sd shutdown time output hi-z 80 ns v ih_sd shutdown pin voltage high part guaranteed to be powered on l 1.3 v v il_sd shutdown pin voltage low part guaranteed to be powered off l 0.6 v t wakeup wake-up time from shutdown v od = 100mv, output valid 100 ns note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: reverse biased esd protection diodes exist on all input, shutdown, latching/hysteresis and output pins. if the voltage on these pins goes 300mv beyond either supply rail, the current should be limited to less than 10ma. this parameter is guaranteed to meet specification through design and/or characterization. it is not production tested. note 3: a heat sink may be required to keep the junction temperature below the absolute maximum rating. this parameter is guaranteed to meet specified performance through design and/or characterization. it is not production tested. note 4: the ltc6752i/ltc6752-1i/ltc6752-2i/ltc6752-3i/ltc6752 - 4i are guaranteed to meet specified per formance from C40c to 85c. the ltc6752h/ltc6752-1h/ltc6752-2h/ltc6752-3h/ltc6752-4h are guaranteed to meet specified performance from C40c to 125c. note 5: total output supply voltage range is guaranteed by the psrr _v dd test. total input supply voltage range for the ltc6752-2, ltc6752-3 and ltc6752-4 is guaranteed by the psrr_v cc test. for the ltc6752 and ltc6752-1, the supply voltage range is guaranteed by the psrr_v cc test. the ltc6752mp is guaranteed to meet specified performance from C55c to 125c. note 6: both hysteresis and offset are measured by determining positive and negative trip points (input values needed to change the output in the opposite direction). hysteresis is defined as the difference of the two trip points and offset as the average of the two trip points. note 7: guaranteed by cmrr test. note 8: propagation delays are measured with a step size of 150mv. note 9: propagation delay skew is defined as the difference of the propagation delays for positive and negative steps for the ltc6752, ltc6752-1, ltc6752-2 and ltc6752-4, and the difference in propagation delays between the complementary outputs for the ltc6752-3. note 10: latch setup time is defined as the minimum time before the le/hyst pin is asserted low for an input signal change to be acquired and held at the output. latch hold time is defined as the minimum time before an input signal change for a high to low transition on the le/hyst pin to prevent the output from changing. see figure 7 for a graphical definition of these terms. note 11: toggling is defined to be valid if the output swings as follows: from 10% of v dd - v ee to 90% of v dd - v ee for the ltc6752-2/ ltc6752-3/ltc6752-4, and from 10% of v cc - v ee to 90% of v cc - v ee for the ltc6752/ltc6752-1. it is tested with a 1k load to v cm note 12: the devices have effectively infinite gain when hysteresis is enabled. ltc 6752/ ltc 6752-1/ ltc 6752 -2/ ltc 6752-3/ ltc 6752 -4 6752fc
10 for more information www.linear.com/ltc6752 typical p er f or m ance c harac t eris t ics d c input bias current vs differential input voltage input hysteresis vs le/hyst pin voltage le/hyst pin i-v characteristics input differential voltage (v) ?5.4 bias current (a) 1.0 0.5 ?0.5 ?1.5 ?2.5 0 ?1.0 ?2.0 ?3.0 ?3.5 ?0.6 4.2 ?3.0 1.8 6752 g07 5.4 ?1.8 3.0 ?4.2 0.6 v cc = 5v v dd = 2.5v v cm = 2.5v ?in +in le /hyst voltage (v) 0.75 hysteresis (mv) 50 40 20 30 10 0 1.50 1.25 6752 g08 1.75 1.00 le /hyst pin voltage (v) ?0.3 le/hyst pin current (a) 200 150 0 100 50 ?50 ?100 4.5 1.3 2.1 2.9 3.7 6752 g09 5.3 0.5 v cc = 2.5v v cc = 5v input offset voltage and hysteresis vs input common mode input bias current vs temperature input bias current vs common mode voltage input offset voltage and hysteresis vs temperature input offset voltage and hysteresis vs v cc voltage input offset voltage and hysteresis vs v dd voltage v cc = v dd = 2.5v, c load = 5pf, v overdrive = 50mv, v cm = 300mv ,t a = 25 c unless otherwise noted. v cc v dd conditions applicable only to the ltc6752- 2/ltc6752- 3/ ltc6752- 4. temperature (c) ?55 offset/hysteresis (mv) 8 6 4 0 2 ?2 ?4 25 105 ?15 65 6752 g01 125 5 85 ?35 45 v hyst v os input common mode voltage (v) offset, hysteresis (mv) 6752 g04 hysteresis offset ?0.2 7 ?2 4 2 6 5 3 1 ?1 ?3 0 1.0 1.8 0.2 1.4 2.2 2.6 0.6 input common mode voltage (v) input bias current (a) 6752 g06 v in = v os ?0.2 0.5 ?1.0 0 ?0.5 ?1.5 ?2.0 1.0 1.8 0.2 1.4 2.2 2.6 0.6 0.8 0.6 0.2 ?0.4 ?0.8 ?1.2 0.4 ?0.2 ?0.6 ?1.0 0 ?1.4 temperature (c) ?55 input bias current (a) 25 105 ?15 65 6752 g05 125 5 85 ?35 45 v cm = 2.2v v cm = 300mv v cc voltage (v) 2.45 offset, hysteresis (mv) 6 5 4 2 3 1 0 4.55 3.85 6752 g02 5.25 3.15 hysteresis offset v dd voltage (v) 1.6 offset, hysteresis (mv) 7 6 5 4 2 3 1 0 3.1 2.6 6752 g03 3.6 2.1 hysteresis offset ltc 6752/ ltc 6752-1/ ltc 6752 -2/ ltc 6752-3/ ltc 6752 -4 6752fc
11 for more information www.linear.com/ltc6752 typical p er f or m ance c harac t eris t ics d c supply current vs temperature (ltc6752/ltc6752-1/ltc6752-2/ ltc6752-4) supply current vs temperature (ltc6752-3) output short-circuit current vs temperature output low voltage vs load current output high voltage vs sourcing current output high/low voltage vs temperature v cc = v dd = 2.5v, c load = 5pf, v overdrive = 50mv, v cm = 300mv ,t a = 25 c unless otherwise noted. v cc v dd conditions applicable only to the ltc6752- 2/ ltc6752 -3/ ltc6752 -4. 80 60 20 ?40 40 ?20 ?60 0 ?80 temperature (c) ?55 short-circuit current (ma) 25 105 ?15 65 6752 g10 125 5 85 ?35 45 v cc = 5v, v dd = 1.8v v cc = v dd = 2.5v v cc = v dd = 3.3v sourcing sinking 5.0 temperature (c) ?55 supply current (ma) 25 105 ?15 65 6752 g14 125 5 85 ?35 45 4.5 4.0 3.0 2.0 1.0 3.5 2.5 1.5 i vcc (ltc6752-2/ltc6752-4) i vdd (ltc6752-2/ltc6752-4) i total (ltc6752-2/ltc6752-4) i cc (ltc6752/ltc6752-1) 7 temperature (c) ?55 supply current (ma) 25 105 ?15 65 6752 g15 125 5 85 ?35 45 6 5 3 1 4 2 i vcc i vdd i total sinking current (ma) 0 output low voltage (v) 4.5 4.0 3.0 2.0 1.0 3.5 2.5 1.5 0.5 0 20 40 10 30 6752 g11 45 15 35 5 25 v cc = 2.5v v dd = 2.5v v cc = 5v v dd = 1.8v v cc = 3.3v v dd = 3.3v measured from v ee sourcing current (ma) 0 output voltage relative to v dd (v) ?4.5 ?4.0 ?3.0 ?2.0 ?1.0 ?3.5 ?2.5 ?1.5 ?0.5 0 20 70605040 10 30 6752 g12 80 v cc = 2.5v v dd = 2.5v v cc = 5v v dd = 1.8v v cc = 3.3v v dd = 3.3v 300 temperature (c) ?55 output high/low voltage (mv) 25 105 ?15 65 6752 g13 125 5 85 ?35 45 250 200 100 0 150 50 v oh v ol source/sink current = 8ma measured from v dd measured from v ee supply current vs supply voltage (ltc6752/ltc6752-1/ltc6752-2/ ltc6752-4) supply current vs supply voltage (ltc6752-3) supply current vs input common mode voltage ( ltc6752/ ltc6752 -1/ ltc6752-2/ltc6752-4) 6 supply voltage (v) 2.45 supply current (ma) 3.35 2.75 6752 g16 3.65 3.05 5 3 0 1 4 2 v cc = v dd i vcc (ltc6752-2/ltc6752-4) i vdd (ltc6752-2/ltc6752-4) i total (ltc6752-2/ltc6752-4) i cc (ltc6752/ltc6752-1) 8 7 6 supply voltage (v) 2.45 supply current (ma) 3.35 2.75 6752 g17 3.65 3.05 5 3 0 1 4 2 i vcc v cc = v dd i vdd i total 4.85 4.80 4.75 4.70 4.65 4.60 4.55 4.50 input common mode voltage (v) ?0.2 total supply current i vcc + i vdd (ma) 1.9 0.5 6752 g18 2.6 1.2 4.45 ltc 6752/ ltc 6752-1/ ltc 6752 -2/ ltc 6752-3/ ltc 6752 -4 6752fc
12 for more information www.linear.com/ltc6752 typical p er f or m ance c harac t eris t ics d c v cc = v dd = 2.5v, c load = 5pf, v overdrive = 50mv, v cm = 300mv ,t a = 25 c unless otherwise noted. v cc v dd conditions applicable only to the ltc6752- 2/ltc6752- 3/ ltc6752- 4. supply current vs temperature, shutdown (ltc6752-2) supply current vs temperature, shutdown (ltc6752-3) shdn pin i-v characteristics total supply current vs shdn pin voltage (ltc6752-2) total supply current vs shdn pin voltage (ltc6752-3) supply current vs input common mode voltage (ltc6752-3) 700 temperature (c) ?55 shutdown supply current (a) 25 105 ?15 65 6752 g23 125 5 85 ?35 45 600 500 300 100 400 200 i vcc i vdd i total 700 temperature (c) ?55 shutdown supply current (a) 25 105 ?15 65 6752 g24 125 5 85 ?35 45 600 500 300 100 400 200 iv cc iv dd i total voltage between shdn pin and v ee (v) ?0.3 shdn pin current (a) 2 0 ?4 ?10 ?14 ?2 ?8 ?12 ?6 ?16 2.1 4.5 6752 g20 5.3 1.3 3.7 0.5 2.9 v cc = 5v v cc = 2.5v 5.0 shdn pin voltage (v) ?0.3 total supply current (ma) 1.7 0.7 6752 g21 2.7 1.2 0.2 2.2 4.5 4.0 3.5 3.0 2.5 2.0 1.5 0.5 1.0 0 6.45 6.40 6.35 6.30 6.25 6.20 6.15 input common mode voltage (v) ?0.2 total supply current i vcc + i vdd (ma) 1.9 0.5 6752 g19 2.6 1.2 6.10 7 6 5 shdn pin voltage (v) ?0.3 total supply current (ma) 1.7 0.7 6752 g22 2.7 1.2 0.2 2.2 4 3 2 1 0 ltc 6752/ ltc 6752-1/ ltc 6752 -2/ ltc 6752-3/ ltc 6752 -4 6752fc
13 for more information www.linear.com/ltc6752 typical p er f or m ance c harac t eris t ics ac v cc = v dd = 2.5v, c load = 5pf, v overdrive = 50mv, v cm = 300mv, t a = 25c, transient input voltage 10mhz, 150mv p-p square wave unless otherwise noted. v cc v dd conditions applicable only to the ltc6752-2/ltc6752-3/ltc6752 -4. propagation delay vs input stage supply voltage rise/fall times vs capacitive load propagation delay vs output stage supply voltage toggle rate vs input amplitude, ltc6752/ltc6752-1/ltc6752-2/ ltc6752-4 propagation delay vs capacitive load toggle rate vs input amplitude, ltc6752-3 propagation delay vs input overdrive propagation delay vs common mode voltage propagation delay vs temperature overdrive (mv) propagation delay (ns) 6752 g25 10 5.0 4.0 3.0 4.5 3.5 2.5 2.0 50 80 3020 60 100 120 70 90 110 40 tpd hl tpd lh v cc = 5v, v dd = 1.8v v cc = 2.5v, v dd = 2.5v v cc voltage (v) 2.45 propagation delay (ns) 3.00 2.95 2.90 2.75 2.65 2.80 2.70 2.85 2.60 3.65 4.85 6752 g28 5.25 3.25 4.45 2.85 4.05 tpd lh tpd hl 3.5 load capacitance (pf) 0 rise/fall time (ns) 20 10 6752 g31 15 5 3.0 2.0 1.0 0 2.5 1.5 0.5 t rise t fall v cc = 5v, v dd = 1.8v v cc = 2.5v, v dd = 2.5v 20 200 2000 360 input amplitude (mv p-p ) toggle rate (mhz) 6752 g32 160 180 200 220 240 260 280 300 320 340 v cm = 1v r l = 1k v cc = 5v, v dd = 1.8v v cc = 2.5v, v dd = 2.5v v cc = 3.3v, v dd = 3.3v 20 200 2000 300 input amplitude (mv p-p ) toggle rate (mhz) 6752 g33 140 160 180 200 220 240 260 280 v cm = 1v r l = 1k v cc = 5v, v dd = 1.8v v cc = 2.5v, v dd = 2.5v v cc = 3.3v, v dd = 3.3v v dd voltage (v) 1.6 propagation delay (ns) 3.7 3.5 3.3 2.7 2.9 3.1 2.5 2.2 3.4 6752 g29 3.6 2.0 3.23.0 1.8 2.4 2.6 2.8 tpd lh tpd hl 4.2 4.0 load capacitance (pf) 0 propagation delay (ns) 20 10 6752 g30 15 5 3.8 3.6 3.2 2.8 2.4 3.4 3.0 2.6 tpd hl tpd lh v cc = 5v, v dd = 1.8v v cc = 2.5v, v dd = 2.5v 4.1 temperature (c) ?55 propagation delay (ns) 25 105 ?15 65 6752 g27 125 5 85 ?35 45 3.9 3.7 3.3 2.9 2.5 3.5 3.1 2.7 tpd hl tpd lh v cc = 5v, v dd = 1.8v v cc = 2.5v, v dd = 2.5v input common mode voltage (v) propagation delay (ns) 6752 g26 ?0.2 3.5 3.0 2.5 1.0 1.8 0.2 1.4 2.2 2.6 0.6 tpd, output falling (tpd hl ) tpd, output rising(tpd hl ) ltc 6752/ ltc 6752-1/ ltc 6752 -2/ ltc 6752-3/ ltc 6752 -4 6752fc
14 for more information www.linear.com/ltc6752 typical p er f or m ance c harac t eris t ics ac output toggle waveform, ltc6752-2 output toggle waveforms q and q, ltc6752-3 toggle rate vs capacitive load, ltc6752-3 toggle rate vs temperature , ( ltc6752/ ltc6752- 1/ltc6752- 2/ltc6752- 4) toggle rate vs temperature, ltc6752-3 output jitter vs input amplitude toggle rate vs capacitive load, ( ltc6752/ ltc6752- 1/ltc6752- 2/ ltc6752- 4) v cc = v dd = 2.5v, c load = 5pf, v overdrive = 50mv, v cm = 300mv, t a = 25c, transient input voltage 10mhz, 150mv p-p square wave unless otherwise noted. v cc v dd conditions applicable only to the ltc6752-2/ ltc6752-3/ltc6752-4. 350 temperature (c) ?55 toggle rate (mhz) 25 105 ?15 65 6752 g34 125 5 85 ?35 45 150 170 190 210 230 250 270 290 310 330 r l = 1k v in = 100mv p-p sinusoid v cc = 5v, v dd = 1.8v v cc = 2.5v, v dd = 2.5v v cc = 3.3v, v dd = 3.3v temperature (c) ?55 toggle rate (mhz) 25 105 ?15 65 6752 g35 125 5 85 ?35 45 150 170 190 210 230 250 270 290 r l = 1k v in = 100mv p-p sinusoid v cc = 5v, v dd = 1.8v v cc = 2.5v, v dd = 2.5v v cc = 3.3v, v dd = 3.3v 500 450 load capacitance (pf) 0 toggle rate (mhz) 20 10 6752 g36 15 5 400 300 200 100 350 250 150 v cc = 5v, v dd = 1.8v v cc = 2.5v, v dd = 2.5v r l = 1k v in = 100mv p-p sinusoid v cc = 3.3v, v dd = 3.3v 380 330 load capacitance (pf) 0 toggle rate (mhz) 20 10 6752 g37 15 5 280 180 80 230 130 v cc = 5v, v dd = 1.8v v cc = 2.5v, v dd = 2.5v r l = 1k v in = 100mv p-p sinusoid v cc = 3.3v, v dd = 3.3v input amplitude (mv p-p ) 0 rms output jitter (ps) 16 14 12 6 2 8 4 10 0 300 600 6752 g38 700 200 500 100 400 v cc = 5v, v dd = 1.8v 100mhz sinosoidal input jitter bandwidth: 10hz to 50mhz v cc = 2.5v, v dd = 2.5v v cc = 3.3v, v dd = 3.3v 2ns/div 6752 g39 500mv/div ltc6752-2 v cc = v dd = 2.5v c l = 5pf 200mhz 2ns/div 6752 g40 500mv/div ltc6752-3 v cc = v dd = 2.5v c l = 5pf 200mhz ltc 6752/ ltc 6752-1/ ltc 6752 -2/ ltc 6752-3/ ltc 6752 -4 6752fc
15 for more information www.linear.com/ltc6752 p in func t ions +in: positive input of the comparator. the voltage range of this pin can go from v ee to v cc . Cin: negative input of the comparator. the voltage range of this pin can go from v ee to v cc . v cc : positive supply voltage for the ltc6752/ltc6752-1, positive supply voltage for the input stage of the ltc6752-2/ltc6752-3/ltc6752-4. v dd : positive supply voltage for the output stage of the ltc6752-2/ltc6752-3/ltc6752-4. typically the voltage is from 1.71v to 3.5v. see the section high speed board design techniques for proper power supply layout and bypassing. v ee : negative power supply, normally tied to ground. this can be tied to a voltage other than ground as long as the constraints for total supply voltage relative to v cc (and v dd for separate supply operation) are maintained. shdn: active low comparator shutdown, threshold is 0.6v above v ee . the comparator is enabled when this pin is left unconnected. le/hyst: this pin allows the user to adjust the compara - tors hysteresis as well as latch the output state if the pin voltage is taken within 300mv above v ee . hysteresis can be increased or disabled by voltage, current or a resistor to v ee . leaving the pin unconnected results in a typical hysteresis of 5mv. q: comparator output. q is driven high when +in > Cin and driven low when +in < Cin. q : comparator complementary output ( available on ltc6752-3 only). logical inversion of q. ltc 6752/ ltc 6752-1/ ltc 6752 -2/ ltc 6752-3/ ltc 6752 -4 6752fc
16 for more information www.linear.com/ltc6752 b lock diagra m v cc v cc v ee v ee 6752 bd ? + ? + v ee v cc v ee v ee ?in v cc v ee v cc +in ? + input stage hysteresis stage v dd v ee ? + gain stage output driver stage q le/hyst shdn le /hyst pin interface 20k 1.25v 350k + + + ? figure 1. ltc6752/ltc6752-1/ltc6752-2/ltc6752-4 block diagram ltc 6752/ ltc 6752-1/ ltc 6752 -2/ ltc 6752-3/ ltc 6752 -4 6752fc
17 for more information www.linear.com/ltc6752 a pplica t ions i n f or m a t ion circuit description the block diagram is shown in figure 1. there are dif - ferential inputs (+in, C in), a negative power supply (v ee ), two positive supply pins: v cc for the input stage and v dd for the output stage, an output pin (q), a pin for latching and adjusting hysteresis (le/hyst), and a pin to put the device in a low power mode (shdn). in the ltc6752 and ltc6752-1, the two positive supply pins are bonded together and referred to as v cc . the signal path consists of a rail-to-rail input stage , an intermediate gain stage, and an output stage driving a pair of complementary fets capable of taking the output pin to either supply rail . a latching/ hysteresis interface block allows the user to latch the output state and/or remove or adjust the comparator input hysteresis. all of the internal signal paths make use of low voltage swings for high speed at low power. the ltc6752-3 has an additional inverted output stage (not shown) for a complementary logic output signal. power supply configurations the ltc6752 - 2/ltc6752- 3/ltc6752 -4 have separate positive supply pins for the input and output stages that allow for separate voltage ranges for the analog input, and the output logic. figure 2 shows a few possible con - figurations. for reliable and proper operation, the input supply pin should be between 2.45 v and 5.25v above the negative supply pin , and the output supply pin should be between 1.71 v and 3.5v above the negative supply pin. there are no restrictions regarding the sequence in which the supplies are applied , as long as the absolute-maximum ratings are not violated. the ltc6752 and ltc6752-1 have only one positive sup - ply pin. the supply voltage should be between 2.45v and 3.5 v for proper and reliable operation. input v oltage range and offset the ltc6752 family uses a rail-to-rail input stage that consists of a pnp pair and an npn pair that are active over different input common mode ranges. the pnp pair is ac - tive for inputs between v ee C 0.2 v and approximately v cc C 1.5v ( low common mode region of operation). the npn pair is active for inputs between approximately v cc C 1v and v cc + 0.1v ( high common mode region of operation). partial activation of both pairs occurs when one input is in the low common mode region of operation and the other input is in the high common mode region of operation, or either of the inputs is between approximately v cc C 1.5v and v cc C 1v ( transition region). the device has small, trimmed offsets as long as both inputs are completely in the low or high common mode region of operation. in the transition region, the offset voltage may increase. applications that require good dc precision should avoid the transition region. input bias current when both inputs are in the low common mode region, the input bias current is negative, with current flowing out of the input pins . when both inputs are in the high common mode region, the input bias current is positive, with current flowing into the input pins. the input stage has been designed to accommodate large differential input voltages without large increases in input bias current. with one input at the positive input supply rail and the other input at the negative supply rail, the magnitude of the input bias currents at either pin is typically less than 3.5a. figure 2. typical power supply configurations (applicable to the ltc6752-2/ltc6752-3/ltc6752-4) ? + v cc v dd 3v3v 6752 f02 q v ee 0v (a) single supply ?in +in ? + v cc v dd 1.8v5v q v ee 0v (b) output supply < input supply ?in +in ? + v cc v dd 3.5v2.5v q v ee 0v (c) output supply > input supply ?in +in ? + v cc v dd 0v2.5v q v ee ?2.5v (d) negative output logic ?in +in ltc 6752/ ltc 6752-1/ ltc 6752 -2/ ltc 6752-3/ ltc 6752 -4 6752fc
18 for more information www.linear.com/ltc6752 a pplica t ions i n f or m a t ion input protection the input stage is protected against damage from condi - tions where the voltage on either pin exceeds the supply voltage ( v cc to v ee ) without external protection. external input protection circuitry is only needed if input currents can exceed the absolute maximum rating. for example, if an input is taken beyond 300mv of either the positive or negative supply, an internal esd protection diode will conduct and an external resistor should be used to limit the current to less than 10ma. outputs the ltc6752 family has excellent drive capability . the comparators can deliver typically 22ma output current for an output supply of 2.5v, and 39ma output current for a 3.3v output supply. attention must be paid to keep the junction temperature of the ic below 150c should the output have a continuous short-circuit condition. logic drive capability the ltc6752 family has been designed to drive cmos logic with a supply of 3.3v, 2.5v and 1.8v. for device reli - ability, the output power supply (v dd ) should not be higher than 3.6 v above the negative supply. when v dd is 3v or higher the cmos outputs of the ltc6752 family provide valid ttl logic threshold levels and can easily interface with ttl logic devices operating with a 5v supply. this is possible because all of the threshold levels associated with ttl logic (v ih /v il /v oh /v ol ) are less than or equal to 2.4v capacitive loads the ltc6752 family can drive capacitive loads. transient performance parameters in the electrical characteristics tables and typical characteristics section are for a load of 5pf, corresponding to a standard ttl /cmos load. the devices are fully functional for larger capacitive loads, however speed performance will degrade . the graphs titled propagation delay vs capacitive load and toggle rate vs capacitive load illustrate the impact of changes to the total capacitive load. for optimal speed performance, output load capacitance should be reduced as much as possible . esd the ltc6752 family members have reverse-biased esd protection diodes on pins as shown in figure 1. there are additional clamps between the positive and negative supplies that further protect the device during esd strikes. hot-plugging of the device into a powered socket is not recommended since this can trigger the clamp resulting in large currents flowing between the supply pins. hysteresis comparators have very high open-loop gain . with slow input signals that are close to each other, input noise can cause the output voltage to switch randomly. this can be addressed by hysteresis which is positive feedback that increases the trip point in the direction of the input signal transition when the output switches. this pulls the inputs away from each other, and prevents continuous switching back and forth. the addition of positive feedback also has the effect of making the small signal gain infinite around the trip points. hysteresis is designed into most comparators and the ltc6752 family has adjustable hysteresis with a default hysteresis of 5mv. the input-output transfer characteristic is illustrated in figure 3 showing the definitions of v os and hyst based upon the two measurable trip points. in some cases, additional noise immunity is required above what is provided by the nominal 5mv hysteresis. figure 3 v oh v ol 0 v os = 6752 f03 v out v os v trip + v hyst (= v trip + ? v trip ? ) ?v in = v in + ? v in ? v trip + + v trip ? 2 v trip ? for v trip + = 3mv, v trip ? = ?2mv, v os = 0.5mv, v hyst = 5mv ltc 6752/ ltc 6752-1/ ltc 6752 -2/ ltc 6752-3/ ltc 6752 -4 6752fc
19 for more information www.linear.com/ltc6752 a pplica t ions i n f or m a t ion conversely, when processing small or fast differential sig - nals, hysteresis may need to be eliminated . the ltc6752 -1/ ltc6752- 2/ltc6752 -3 provide a hysteresis pin, le/ hyst, that can be used to increase the internal hysteresis, completely remove it, or enable the output to latch. for these 3 options of the ltc6752, the internal hysteresis is disabled when the le/hyst pin voltage is above 1.7v. although eliminating hysteresis does reduce the voltage gain of the comparator to a finite value, in many cases it will be high enough (typically 6000v/v) to process small input signals. the output will latch when the le/hyst pin voltage is below 0.3v. the internal hysteresis will increase as the voltage of the pin is adjusted from its default open circuit value of 1.25v to 800mv. the le/ hyst pin can be modeled as a 1.25 v voltage source in series with a 20k resistor. the simplest method to increase the internal hysteresis is to connect a single resistor as shown in figure 4 between the le/hyst pin and v ee to adjust hysteresis. figure 5 shows how hysteresis typically varies with the value of the resistor. in addition to adjusting hysteresis using the le/hyst pin, additional hysteresis can be added using positive feedback from the output back to the positive input, as shown in figure 6. the offset (with respect to the input signal) and hysteresis become v os _ fb = v dd + v ee ( ) 2 r1 r1 + r2 + v ref r2 r1 + r2 ? v os ? v oh 2 r1 r1 + r2 + v ol r2 r1 + r2 ? ? (1) v hyst _ fb = v dd ? v ee ( ) r1 r1 + r2 + v ol r2 r1 + r2 + v oh r1 r1 + r2 + v hyst ? ? (2) v os_fb and v hyst_fb denote the values of offset and hysteresis with positive feedback present. v hyst denotes the hysteresis of the device without positive feedback. for light loads, v oh ( output swing high) and v ol (output swing low) are typically a few mv (typically are less than 10mv for a 500a load). on a 3.0v total supply with v ee = 0v, an increase in hysteresis of approximately 300mv can be obtained with v ref = 1.25v, r 2 = 4.53k , r 1 = 511, with an induced offset of approximately 1.275v. figure 4. adjusting hysteresis using an external resistor at the le/hyst pin figure 5. hysteresis vs control resistor figure 6. additional hysteresis using positive feedback 6752 f04 ? + v cc v dd q v ee le/hyst r ?in +in 6752 f06 ? + v cc v ref signal v dd q v ee r2 r1 50 control resistance (k) 30 hysterisis (mv) 230 430 130 330 6752 f05 480 180 380 80 280 0 5 10 15 20 25 30 35 40 45 v cc = v dd = 2.5v v cm = 0.3v t a = 25c control resistor connected between le/hyst pin and v ee ltc 6752/ ltc 6752-1/ ltc 6752 -2/ ltc 6752-3/ ltc 6752 -4 6752fc
20 for more information www.linear.com/ltc6752 a pplica t ions i n f or m a t ion latching the internal latch of the ltc6752- 1/ltc6752- 2/ltc6752 -3 retains the output state when the le/ hyst pin is taken to less than 300mv above the negative supply. figures 7 a to 7e illustrate the latch timing definitions. the latch setup time is defined as the time for which the input should be stable before the latch pin is asserted low to ensure that the correct state will be held at the output. the latch hold time is the interval after which the latch pin is asserted in which the input signal must remain stable for the output to be the correct state at the time latch was asserted. the latch to output delay (t pl ) is the time taken for the output to return to input control after the latch pin is released. latching is disabled if the le/hyst pin is left floating. both outputs of the ltc6752-3 are latch controlled simultaneously. 6752 f07a +in ? ?in t > t setup t pd q le/hyst 6752 f07d +in ? ?in t > t hold t pd q le/hyst t > t setup 6752 f07e +in ? ?in t pl q le/hyst 6752 f07c +in ? ?in t < t hold t pd q le /hyst 6752 f07b +in ? ?in t < t setup q le/hyst figure 7a. input state change properly latched figure 7b. input change setup time too short figure 7c. input state not held long enough. wrong output state latched figure 7d. short input pulse properly captured and latched figure 7e. latched output disabled shutdown the ltc6752 -2 and ltc6752 -3 have shutdown pins (shdn, active low) that can reduce the total supply cur - rent to a typical value of 580 a for the ltc6752-2 and 650a for the ltc6752-3 (2.5v supply). when the part is in shutdown, the outputs are placed in a high-impedance state, since pfet and nfet output transistors whose drains ltc 6752/ ltc 6752-1/ ltc 6752 -2/ ltc 6752-3/ ltc 6752 -4 6752fc
21 for more information www.linear.com/ltc6752 a pplica t ions i n f or m a t ion are tied to the output pins are cut off and cannot source / sink any current. the shutdown pin needs to be taken to within 600 mv of the negative supply for the part to shut down. when left floating, the shutdown pin is internally pulled towards the positive supply, and the comparator remains fully biased on. dispersion dispersion is defined as the change in propagation delay for different input conditions. it becomes very crucial in timing sensitive applications. overdrive dispersion from 10mv overdrive to 125mv overdrive is typically less than 1.8ns (150 mv total step size). the graph titled propagation delay vs common mode voltage shows the dispersion due to shifts in input common mode voltage. jitter the ltc6752 family has been designed for low phase noise and jitter. this allows it to be used in applications where high frequency low amplitude sine waves need to be converted to full-logic level square waves with mini - mal additive jitter. the graph titled output jitter vs input amplitude demonstrates the additive jitter of the ltc6752 family for different amplitudes of a sinusoidal input. refer to the electrical characteristics table to see how jitter varies with signal frequency. high speed board design techniques being very high speed devices , members of the ltc6752 family are prone to output oscillations if certain guidelines are not followed at the board level. low impedance supply planes, especially for the v dd and v ee pins, help to reduce supply bounce related oscillations. supply bounce tends to worsen at higher output supply voltages due to larger swings and higher output current drive capability. parasitic feedback between the output and input pins should be minimized. the pinouts of the ltc6752 family members have been arranged to minimize parasitic feedback. input and output traces on the board should be placed away from each other. if that is not possible a ground or supply trace should be used as a guard to isolate them . if possible , a supply / ground trace that is not directly connected to the supply pins of the device, but rather directly connected to the supply terminal of the board, should be used for such a purpose. the positive supply pins should be adequately bypassed to the v ee pin to minimize transients on the supply. low esr and esl capacitors are required due to the high speed nature of the device. even a few nanohenries of parasitic trace inductance in series with the supply bypassing can cause several hundred millivolts of disturbance on the supply pins during output transitions. a 2.2 f capacitor in parallel with multiple low esl, low esr 100 nf capacitors connected as close to the supply pins as possible to minimize trace impedance is recommended. in many applications the v ee pin will be connected to ground. in applications where the v ee pin is not connected to ground, the positive supplies should still be bypassed to v ee . the v ee pin should also then be bypassed to a ground plane with a 2.2 f capacitor in parallel with low esl, low esr 100nf capacitors if possible. for devices with separate positive input and output sup - plies, capacitors should not be placed between the two positive supplies ; otherwise disturbances due to output switching can couple back to the inputs. to minimize supply bounce , the board layout must be made with careful consideration of the supply current return paths. the output current will return back to the supply via the lowest impedance path available . if the terminating connection of the load is easily available on the board, v ee should be bypassed to the terminating connection using 2.2f and 100nf capacitors as described previously. due to the fast rise and fall times of the ltc6752/ ltc6752- 1/ ltc6752 -2/ ltc6752- 3/ltc6752- 4, output traces should be shielded with a low impedance ground plane to minimize electromagnetic interference . due to the complementary nature of its outputs, the ltc6752-3 can provide a first order cancellation of emi effects. when the input slew rate is small, sustained oscillations can occur at the output pin while the input is transitioning due to even one millivolt of ground bounce . for applica - tions where the input slew rate is low, internal hysteresis should not be removed by taking the le/hyst pin high, as the addition of hysteresis makes the comparators more immune to disturbances such as ground bounce. increas - ing hysteresis by adjusting the le/hyst pin voltage or by adding positive feedback as discussed in the section on hysteresis can further improve noise immunity . ltc 6752/ ltc 6752-1/ ltc 6752 -2/ ltc 6752-3/ ltc 6752 -4 6752fc
22 for more information www.linear.com/ltc6752 typical a pplica t ions high speed clock restoration/level translation circuit high speed comparators are often used in digital systems to recover distorted clock waveforms. the separate input/ output supplies feature of the ltc6752-2 allows it to be used in applications where signals need to be shifted from one voltage domain to another. figure 8 shows a circuit that can perform both recovery and level translation functions . in this application, the input clock signal comes from a source operating from 5v, and the signal is required to drive a receiver operating on 1.8 v. the 5 v input supply /1.8 v output supply feature of this part is ideal for such a situation. if the input signal gets distorted and its amplitude severely reduced due to stray capacitance, stray inductance or due to reflections on the transmission line, the ltc6752-2 can be used to convert it into a full scale digital output signal that can drive the receiver. figure 9 shows the input and output waveforms of the ltc6752- 2, used to recover a distorted 150mv p-p 200mhz signal at a common mode of 2.5v with respect to its nega- tive supply , int o a full scale 1.8 v output signal . ac-coupling could have been used at the input of the comparator, how - ever to preserve input duty cycle information dc-coupling may be preferable , and that is where having a wide input common mode range is an advantage. optical receiver circuit the ltc6752, along with a high speed high performance fet input operational amplifier like the ltc6268, can be used to implement an optical receiver as shown in figure 10. figure 11 shows the output of the ltc6268 driving the Cin pin of the ltc6752-2, the +in pin of the ltc6752-2, and the ltc6752-2 output. the photodiode is being driven by a light source of sinusoidally varying intensity. figure 10. optical receiver circuit figure 9 v out , 500mv/div v in , 50mv/div 2ns/div 6752 f09 v ref 3.3v 3.3v 3.3v 3.3v 5.49k 20k ? + ltc6268 0v to 3.3v out 1k 6752 f10 ? + v cc ltc6752-2 v dd v ee le/hyst shdn q 4.53k 0.1f 0.1f 47.6k fci-125 1k figure 8. high speed clock restoration/level translation/level shifting circuit ? + v cc v dd v ee + 1.8v v ee v ee + 1.8v v ee + 5v 6752 f08 200mhz clock signal attenuated 150mv p-p 200mhz, v cm = 2.5v ~1.8v p-p 200mhz, clock signal long trace v ee v ref = v ee + 2.5v clock/data receiver ltc6752-2 v ee clock/data source ltc 6752/ ltc 6752-1/ ltc 6752 -2/ ltc 6752-3/ ltc 6752 -4 6752fc
23 for more information www.linear.com/ltc6752 typical a pplica t ions comparator u2 timing resistor r timing capacitor c 3.3v 100pf 2k 22k ? + 6.65k 22k v cc 3.3v comparator u1 3.3v 15k output 3.3v 100ns pulse ? + v cc ltc6752-2 input 15mv to 3.3v pulse minimum pulse width 5ns v dd v ee le/hyst shdn out 49.9 1000pf 1k sod-123 osa 49.9 z out = 50 ltc6752-2 v dd v ee le/hyst shdn out figure 11 figure 12 figure 13 500mv/div in ? in + out 0 0.5 1.0 1.5 2.0 2.5 4.0 3.5 3.0 4.5 5.0 10ns/div 90 80706050403020100 6752 f11 output, 2v/div input, 20mv/div 20ns/div 6752 f13 pulse stretcher circuit/monostable multivibrator for detecting short pulses from a single sensor, a pulse stretcher is often required. the circuit of figure 12 acts as a one-shot, stretching the width of an incoming pulse to a consistent ~100ns . the circuit works as follows : compara - tor u1 functions as a threshold detector, and comparator u 2 functions as a one-shot. comparator u1 is biased with a threshold of 11 mv to overcome comparator and system offsets, and establish a low output in the absence of an input signal. an input pulse causes the output of u1 to go high, which then causes the output of u2 to go high. the output of u2 is fed back to the input of the 1st compara - tor, timing capacitor c now begins charging through r. after 100ns, u2 goes low, allowing u1 also to go low. a new pulse at the input of u2 can now restart the process. timing capacitor c can be increased without limit for longer output pulses. figure 13 shows input and output waveforms for the pulse stretcher circuit. ltc 6752/ ltc 6752-1/ ltc 6752 -2/ ltc 6752-3/ ltc 6752 -4 6752fc
24 for more information www.linear.com/ltc6752 typical a pplica t ions common mode rejecting line receiver differential electrical signals being transmitted over long cables are often attenuated . electrical noise on the cables can take the form of common mode signals. the ltc6752 comparators can be used to retrieve attenu - ated differential signals that have been corrupted by high frequency common mode noise , as shown in figure 14. figure 15 shows an ltc6752-2 retrieving a 200mhz, 200mv p-p differential input signal that has 2.5v of random, common mode noise superimposed on it. the input supply (v cc ) used was 5v and the output supply used was 2.7v. a small amount of modulation is seen at the output due to a small amount of differential modulation at the inputs, which causes cycle to cycle variations in propagation delay. fast event capture the circuit shown in figure 16 can be used to capture small and fast events. the comparator output is used to signal the latch pin and hold the output in the high state . the circuit will reset when the reset line is low. an open drain 1.5 ns nand gate is used to both invert the output signal and is used to mux in the reset line from the supervising circuit . one important feature of the nand is that it is open drain which allows the comparator to use either its default 5mv of hysteresis or a user programmed hysteresis. the latch recovery time of this circuit is roughly 210 ns and is dominated by the time constant created by the capacitance seen at the output of the nand gate and the 20k series resistance of the le/hyst pin. the waveforms are shown in figure 17. figure 14 figure 15 ? + v cc = 5v v dd = 2.7v q 6752 f14 small differential signal with large common mode component v ee +in ?in ltc6752-2 500mv/div ?in +in q 50ns/div 6752 f15 figure 16 figure 17 500mv/div 50ns/div 6752 f17 reset input ref out 3.3v 6752 f16 ? + v cc ltc6752-2 v dd v ee le/hyst shdn q 2.2f 0.1f 0.1f 200 182k event in 50mv, 10ns input reset 3.3v ref nxp 74lvc1g38 out ltc 6752/ ltc 6752-1/ ltc 6752 -2/ ltc 6752-3/ ltc 6752 -4 6752fc
25 for more information www.linear.com/ltc6752 1.50 ? 1.75 (note 4) 2.80 bsc 0.30 ? 0.45 typ 5 plcs (note 3) datum ?a? 0.09 ? 0.20 (note 3) s5 tsot-23 0302 pin one 2.90 bsc (note 4) 0.95 bsc 1.90 bsc 0.80 ? 0.90 1.00 max 0.01 ? 0.10 0.20 bsc 0.30 ? 0.50 ref note: 1. dimensions are in millimeters 2. drawing not to scale 3. dimensions are inclusive of plating 4. dimensions are exclusive of mold flash and metal burr 5. mold flash shall not exceed 0.254mm 6. jedec package reference is mo-193 3.85 max 0.62 max 0.95 ref recommended solder pad layout per ipc calculator 1.4 min 2.62 ref 1.22 ref s5 package 5-lead plastic tsot-23 (reference ltc dwg # 05-08-1635) p ackage descrip t ion please refer to http://www .linear.com/product/ltc6752#packaging for the most recent package drawings. ltc 6752/ ltc 6752-1/ ltc 6752 -2/ ltc 6752-3/ ltc 6752 -4 6752fc
26 for more information www.linear.com/ltc6752 msop (ms8) 0213 rev g 0.53 0.152 (.021 .006) seating plane note: 1. dimensions in millimeter/(inch) 2. drawing not to scale 3. dimension does not include mold flash, protrusions or gate burrs. mold flash, protrusions or gate burrs shall not exceed 0.152mm (.006") per side 4. dimension does not include interlead flash or protrusions. interlead flash or protrusions shall not exceed 0.152mm (.006") per side 5. lead coplanarity (bottom of leads after forming) shall be 0.102mm (.004") max 0.18 (.007) 0.254 (.010) 1.10 (.043) max 0.22 ? 0.38 (.009 ? .015) typ 0.1016 0.0508 (.004 .002) 0.86 (.034) ref 0.65 (.0256) bsc 0 ? 6 typ detail ?a? detail ?a? gauge plane 1 2 3 4 4.90 0.152 (.193 .006) 8 7 6 5 3.00 0.102 (.118 .004) (note 3) 3.00 0.102 (.118 .004) (note 4) 0.52 (.0205) ref 5.10 (.201) min 3.20 ? 3.45 (.126 ? .136) 0.889 0.127 (.035 .005) recommended solder pad layout 0.42 0.038 (.0165 .0015) typ 0.65 (.0256) bsc ms8 package 8-lead plastic msop (reference ltc dwg # 05-08-1660 rev g) p ackage descrip t ion please refer to http://www .linear.com/product/ltc6752#packaging for the most recent package drawings. ltc 6752/ ltc 6752-1/ ltc 6752 -2/ ltc 6752-3/ ltc 6752 -4 6752fc
27 for more information www.linear.com/ltc6752 1.15 ? 1.35 (note 4) 1.80 ? 2.40 0.15 ? 0.30 6 plcs (note 3) sc6 sc70 1205 rev b 1.80 ? 2.20 (note 4) 0.65 bsc pin 1 0.80 ? 1.00 1.00 max 0.00 ? 0.10 ref note: 1. dimensions are in millimeters 2. drawing not to scale 3. dimensions are inclusive of plating 4. dimensions are exclusive of mold flash and metal burr 5. mold flash shall not exceed 0.254mm 6. details of the pin 1 identifier are optional, but must be located within the index area 7. eiaj package reference is eiaj sc-70 8. jedec package reference is mo-203 variation ab 2.8 bsc 0.47 max 0.65 ref recommended solder pad layout per ipc calculator 1.8 ref 1.00 ref index area (note 6) 0.10 ? 0.18 (note 3) 0.26 ? 0.46 gauge plane 0.15 bsc 0.10 ? 0.40 sc6 package 6-lead plastic sc70 (reference ltc dwg # 05-08-1638 rev b) p ackage descrip t ion please refer to http://www .linear.com/product/ltc6752#packaging for the most recent package drawings. ltc 6752/ ltc 6752-1/ ltc 6752 -2/ ltc 6752-3/ ltc 6752 -4 6752fc
28 for more information www.linear.com/ltc6752 3.00 0.10 (4 sides) recommended solder pad pitch and dimensions 1.65 0.05 (4 sides) note: 1. drawing conforms to jedec package outline mo-220 variation (weed-1) 2. drawing not to scale 3. all dimensions are in millimeters 4. dimensions of exposed pad on bottom of package do not include mold flash. mold flash, if present, shall not exceed 0.15mm on any side 5. exposed pad shall be solder plated 6. shaded area is only a reference for pin 1 location on the top and bottom of package pin 1 top mark (note 6) 0.40 0.10 bottom view?exposed pad 1.65 0.10 (4-sides) 0.75 0.05 r = 0.115 typ 0.25 0.05 1 pin 1 notch r = 0.20 typ or 0.25 45 chamfer 11 12 2 0.50 bsc 0.200 ref 2.10 0.05 3.50 0.05 0.70 0.05 0.00 ? 0.05 (ud12) qfn 0709 rev ? 0.25 0.05 0.50 bsc package outline ud package 12-lead plastic qfn (3mm 3mm) (reference ltc dwg # 05-08-1855 rev ?) p ackage descrip t ion please refer to http://www .linear.com/product/ltc6752#packaging for the most recent package drawings. ltc 6752/ ltc 6752-1/ ltc 6752 -2/ ltc 6752-3/ ltc 6752 -4 6752fc
29 for more information www.linear.com/ltc6752 information furnished by linear technology corporation is believed to be accurate and reliable . however, no responsibility is assumed for its use. linear technology corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights . r evision h is t ory rev date description page number a 01/15 addition of ltc6752-1 and ltc6752-4 options. sc6 package added. fast event capture added to typical applications. all 2 24 b 06/15 test condition for cmrr_lvcm updated: v cm = v ee C 0.2v to v cc C 1.5v electrical characteristics section updated to show that v le/hyst , r hyst , i ih_le , i il_le specifications apply over the specified temperature range. figure 1 updated to show hysteresis symbol. the latched output disable description and figure 7 corrected to show the latch to output delay (t pl ) instead of latch propagation delay (t pdl ). 3, 6, 8 5, 7, 9 16 20 c 04/17 addition of extended temperature range under features addition of mp, extended temperature part addition of extended temperature range on note 5 updated web links 1 2, 3 9 25 to 28 ltc 6752/ ltc 6752-1/ ltc 6752 -2/ ltc 6752-3/ ltc 6752 -4 6752fc
30 for more information www.linear.com/ltc6752 ? linear technology corporation 2014 lt 0417 rev c ? printed in usa www.linear.com/ltc6752 typical a pplica t ion r ela t e d p ar t s part number description comments high speed comparators lt1715 4ns 150mhz dual comparators 4.6ma at 3v lt1711 high speed rail-to-rail comparators 3v/5v/5v, 4.5ns at 20mv overdrive lt1713/lt1714 single/dual low power rail-to-rail comparators 2.7v/5v/5v, 7ns at 20mv overdrive lt1719/lt1720 dual/quad 4.5ns rail-to-rail output comparators 4ma/comparator, 7ns at 5mv overdrive LT1394 7ns single supply ground sensing comparator 6ma, 800v offset clock buffers/logic converters ltc6957-1/ltc6957-2/ ltc6957-3/ltc6957-4 low phase noise, dual output buffer/driver/logic converter lvpecl/lvds/cmos outputs, additive jitter 45f srms (ltc6957-1) high speed operational amplifiers ltc6252/ltc6253/ ltc6254 single/dual/quad 3.5ma 720mhz 280v/s, 2.75nv/hz, rail-to-rail i/o ltc6246/ltc6247/ ltc6248 single/dual/quad 1ma, 180mhz 90v/s, 4.2nv/hz,rail-to-rail i/o ltc6255/ltc6256/ ltc6257 single/dual/quad 65a, 6.5mhz ltc6240/ltc6241/ ltc6242 18mhz, low noise, cmos rail-to-rail outputs ltc6406 3ghz, differential amplifier/driver rail-to-rail inputs ltc6409 10ghz differential amplifier/adc driver 1.1nv/hz 200mhz clock restoration/level shifting ? + v cc v dd v ee + 1.8v v ee v ee + 1.8v v ee + 5v 6752 ta02a 200mhz clock signal attenuated 150mv p-p 200mhz, v cm = 2.5v ~1.8v p-p 200mhz, clock signal long trace v ee v ref = v ee + 2.5v clock/data receiver ltc6752-2 v ee clock/data source v out , 500mv/div v in , 50mv/div 2ns/div 6752 ta02b v ref ltc 6752/ ltc 6752-1/ ltc 6752 -2/ ltc 6752-3/ ltc 6752 -4 6752fc

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